The I2C™-bus specification published by Philips Semiconductors (I2C™ is Philips trademark) and incorporated herein by reference, is a de facto world standard for providing the physical layer for data communication between a plurality of connected integrated circuits (ICs). The I2C™-bus supports any IC fabrication process and comprises a first wire for carrying serial data (SDA) and a second wire for carrying a serial clock (SCL). The ICs connected to the I2C™-bus are each recognized by a unique address and depending on operation of each of the ICs they may act as transmitters or receivers on the I2C™-bus. The connected ICs may act as slaves or masters, where a master determines when to communicate to a slave, and where the master determines when the slave is to communicate with the master.
The I2C™-bus specification specifies a data frame 10, as shown in FIG. 1a, for communicating data on the I2C™-bus, which data frame requires a “start condition” 12 prior to transmission on the I2C™-bus and consisting of a 7-bit “address” 14 of the receiving IC. The address 14 is followed by a data direction bit 16, where a “0” indicates “WRITE” and a “1” indicates “READ”, and the data frame 10 is terminated by a “stop condition” 18. Subsequent to receiving the data direction bit 16 the I2C™ specification requires the data receiving IC to acknowledge reception of the address 14 and the data direction bit 16 by forwarding an acknowledgement bit 20, accomplished by pulling the first wire of the I2C™-data bus “0”. Following reception of the acknowledgement bit 20 the data transmitting IC initiates transmission of data 22. Transmission of each data byte is followed by further acknowledgement bits from the data receiving IC, shown in FIG. 1a as acknowledgement bit 24 and data 26. Finally, the last data byte 26 is acknowledged by a final acknowledgement bit 28.
In high speed transfer mode a data frame 30, as shown in FIG. 1b, further comprises a further “start condition” 32, an 8-bit “code” 34 and a “not-acknowledgement bit” 36 preceding a “start condition” 38, which replaces the “start condition” 12 described above. In addition, in high speed transfer mode the data bytes are only acknowledged following transmission of the last data byte.
The “stop condition” 18 may be substituted by a further “start condition” 38, so as to allow for a series of data to be forwarded to a plurality of IC slaves and/or masters in one particularly defined mode.
The I2C™-bus provides means for establishing exchange of data in a wide variety of electronic equipment, however, the I2C™-bus specification fails to provide specifications for linking of various types modules of an electronic system having different transport layer requirements. Hence, whenever data is to be transferred over the I2C™-bus there is a need for establishing compatibility between old and added new modules, or modules using different transport layer protocols. That is, when a new set of electronic modules are to be connected with an existing electronic system utilising an I2C™-bus operating in accordance with a first set of data exchange rules the new set of electronic modules is required to communicate in accordance with the first set of data exchange rules when communicating with the existing electronic modules. Thus a series of sets of data exchange rules is required or, alternatively, the oldest set of data exchange rules determines which should be used thereby severely limiting further developments.